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cmos the MC145073 is a dualchannel, 16bit a/d converter intended for use in digital audio systems such as multimedia, dcc, dat, and professional audio applications. it uses a sigmadelta architecture consisting of a secondorder analog modulator and two stages of digital filtering for each channel. the analog modulator samples the input signal at 128 times the output data rate, performs a singlebit quantization, and shapes the quantization noise towards higher frequencies. subsequent onchip digital filters reject most of the shaped quantization noise and lower the data rate. sixteen unique userselectable interfacing modes make the MC145073 compatible with a multitude of application interfacing requirements. a single 5 v supply and a powerdown mode reduce power supply requirements, making the part attractive for portable applications. ? single supply, operating voltage range: 4.5 to 5.5 v ? 128x osr sigmadelta modulator ? 82 db typical s/(n+d) ? analog inputs can be driven as either differential or singleended ? clock input may be 128x, 256x, or 384x the output data rate ? outofrange input signals internally limited ? onchip digital filters: 5th order decimateby32 comb filter 121 tap decimateby4 fir filter ? userselectable digital filter transition bands ? versatile serial digital output interface: configurable as master or slave data can be either left or rightjustified interfaces to dsp56000/1 and tms320 ? dsps i 2 s or japanese interface compatibility cs5326 compatible interface mode multiplexing of two MC145073s accommodated ? powerdown mode consumption: 2.0 mw ? operating temperature range: 40 to 85 c modulator a in(+l) a in(l) comb filter a in(+r) a in(r) modulator comb filter voltage reference clk modes in clk dividers/driver and control logic fir filter fir filter serial interface digital interface this document contains information on a product under development. motorola reserves the right to change or discontinue this product without notice. tms320 is a trademark of texas instruments. order this document by MC145073/d
semiconductor technical data pin assignment dw suffix sog package case 751e ordering information MC145073dw sog package csel1 fsel v ag v dd(d) v dd(a) a in(+l) a in(l) ref vss(a) sub v ss(d) ftp ftp sync sclk a in(+r) a in(r) csel0 i sync i slav i just i doe clk sdo 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 13 11 12 21 22 23 24 1 24 ? motorola, inc. 1997 rev 1 5/97
MC145073 motorola 2 maximum ratings* (voltages referenced to v ss , unless otherwise stated) symbol parameter value unit v dd(a) analog supply voltage 6.0 v v dd(d) digital supply voltage 6.0 v i in dc input current, per pin 20 ma v in(a) analog input voltage v ss(a) 0.3 to v dd(a) + 0.3 v v in(d) digital inputs 0.3 to v dd(d) + 0.3 v t stg storage temperature 65 to 150 c t l lead temperature 1 mm from case for 10 seconds 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the operation ranges, analog specifications, ac electrical characteristics, and dc electrical characteristics tables. operation ranges symbol parameter min max unit note v dd(a) analog supply voltage 4.5 5.5 v v dd(d) digital supply voltage 4.5 5.5 v v in(a) analog input voltage (a in(+l) , a in(l) , a in(+r) , a in(r) ) e 1.9 v pp 1 f clk clk frequency 3.072 18.432 mhz 2 c load capacitive load on any output 0 50 pf t a ambient operating temperature 40 85 c notes: 1. differential inputs greater than 3.8 v pp will overload the modulators. these voltages are subject to the gain error tolerance specifications in the analog specifications table. 2. the internal clock frequency or input sampling frequency is governed by the divide mode and output data rate. the divide mode can be either 1, 2, or 3. the output data rate ranges from 24 khz to 48 khz. the minimum clock frequency of 3.072 mhz is for a 24 khz output rate in the clock divide by 1 mode. the maximum clock frequency of 18.432 mhz is for a 48 khz output rate in the clock divide by 3 mode. dc electrical specifications (voltages referenced to v ss(d) ; full temperature and voltage ranges per operation ranges table, unless otherwise indicated.) symbol parameter min max unit v ih minimum highlevel digital input voltage 0.7 x v dd(d) v v il maximum lowlevel digital input voltage 0.3 x v dd(d) v i in maximum input leakage current 10 m a v oh minimum highlevel digital output voltage (i oh = 20 m a) 4.4 v v ol maximum lowlevel digital output voltage (i ol = 20 m a) 0.1 v i ddu(d) maximum digital power supply current, operating 45 ma i ddd(d) maximum digital power supply current, powerdown 250 m a i ddu(a) maximum analog power supply current, operating 10 ma i ddd(a) maximum analog power supply current, powerdown 150 m a p o power consumption, operating 250 mw p pd power consumption, powerdown 2.0 mw cin maximum input capacitance 20 pf this device contains protection circuitry to guard against damage due to high static volt- ages or electric fields. however, precautions must be taken to avoid applications of any volt- age higher than maximum rated voltages to this highimpedance circuit.
motorola MC145073 3 analog specifications (full temperature, clk = 6.144 mhz in div1, v dd(a) = v dd(d) = 5.0 v, 1007.8 hz fullscale input sinewave, 1.4 v pp @ a in(l) and a in(r) , common mode input voltage = 2.5 v. measured bandwidth is 23 hz to 24 khz, inputs driven differentially per figure 1.) parameter min typ max unit resolution bits 16 bits s/(n+d) 76 82 db dynamic range 85 db total harmonic distortion (vin = f.s.) .003 % gain error 5 % gain drift 50 ppm/ c channel to channel isolation 90 db psrr (v dd(a) ) 60 db psrr (v dd(d) ) 100 db input impedance 40 k w warmup time (for reference and bias circuits) 1 ms digital filter characterization (over full operating ranges per operating ranges table. stated values are for input/output relationships from input of comb filter to output of fir filter.) p output data rate ui n parameter 32 khz 44.1 khz 48 khz unit notes fsel = low fir filter passband 0 to 13.3 0 to 18.3 0 to 20 khz maximum passband ripple 0.1 0.1 0.1 db fir filter transition band 13.3 to 17 18.3 to 23.5 20 to 25.8 khz fir filter rejection (min) 84 84 84 db maximum alias level (figure 3) 86 86 86 db 1, 2 group delay 33 33 33 out clks 3 setting time 49 49 49 out clks 3 fsel = high fir filter passband 0 to 14.5 0 to 20 0 to 21.7 khz maximum passband ripple 0.1 0.1 0.1 db fir filter transition band 14.5 to 18.2 20 to 25.0 21.7 to 27.3 khz fir filter rejection (min) 84 84 84 db maximum alias level (figure 3) 86 86 86 db 1, 2 group delay 33 33 33 out clks 3 setting time 49 49 49 out clks 3 notes: 1. there is no rejection of input signals that are multiples of the sampling frequency (nxclki filter bandwidth, where n = 0, 1, 2, ...). 2. the maximum alias level spec does not apply to input signals in the range of 24 to 25.8 khz in the 48 khz output mode, 22.05 to 23.675 khz in the 44.1 khz output mode, or 16 to 17.2 khz in the 32 khz output mode. 3. one out clk (output clock) is equal in length to 128 internal clks or one sync clock period.
MC145073 motorola 4 + v dd(a) a in(r) r in 1 k w 2 3 6 5 u2a u2b a out(r) a out(+r) + 1 7 1 k w 1 k w v dd(a) + a in(l) r in 1 k w 2 3 6 5 u1a u1b a out(l) a out(+l) + 1 7 v dd(a) 1 k w 1 k w v dd(a) v dd(a) figure 1. input bufferdriver notes: 1. analog signals a in(l) and a in(r) are floating drivers. r out of source is to be equal to r in of resistors. 2. u1, u2 e mc33077.
motorola MC145073 5 *a in(r) *a in(+r) *a in(l) *a in(+l) 1000 pf 0.1 m f 4 v dd(a) 5 v ss(a) 8 v dd(d) 7 v ss(d) 1a in (+l) 2a in (l) 24 a in (+r) 23 a in (r) 22 v ag 3 ref sclk 12 sync 11 sdo 13 fsel 19 csel0 21 csel1 20 clk 14 audio data processor controller mc74hcu04 11.2896 mhz for 44.1 khz user selectable digital states sub 6 i doe 15 i slav 17 i sync 18 i just 16 ftp 9 ftp 10 1000 pf 1000 pf 1000 pf 1 m f 0.1 m f 1 m f 820 k w 22 pf 33 33 33 33 0.1 m f 47 m f v dd(a) v dd(d) 1 m f * for best performance a in(+l) , a in(l) and a in(+r) , a in(r) should be differentially driven. a in(+l) or a in(+r) (and a in(l) or a in(r) ) can be grounded for single ended configuration. circuit in figure 1 depicts input buffer circuit. 22 pf figure 2. MC145073 a/d application circuit
MC145073 motorola 6 0 86 0 24 48 72 96 120 144 168 192 216 240 264 288 input frequency (khz) maximum alias = 86.713 db at 24.0 khz converter gain (db) output data rate = 48 khz, fsel = low 0 86 0 24 48 72 96 120 144 168 192 216 240 264 288 maximum alias = 87.5884 db at 169.125 khz input frequency (khz) converter gain (db) output data rate = 44.1 khz, fsel = high figure 3. digital filter response (wideband) clki = 6.144 mhz 20 0 20 40 60 80 100 0 1224364860728496 response (db amplitude) digital filter response (20 25.8 khz transition band) input frequency (khz) 20 0 20 40 60 80 100 01224364860728496 response (db amplitude) digital filter response (20 24 khz transition band) input frequency (khz) output data rate = 48 khz, fsel = high output data rate = 44.1 khz, fsel = high figure 4. digital filter response (narrowband) clki = 6.144 mhz simulated delays 0 25 50 75 100 125 150 175 200 225 250 time (output clocks) comb filter input comb filter output fir filter output simulated delays time (output clocks) 0 5 10 15 20 25 30 35 40 comb filter input comb filter output fir filter output figure 5. group delay and setting time
motorola MC145073 7 ac electrical specifications (full temperature and voltage ranges per operation ranges table. all timing parameters measured with respect to 30% and 70% of v dd(d ) unless otherwise noted.) figure symbol parameter divide ratio min max unit 6 1/t clk master clock (clk) frequency (note 1) 3.072 18.432 mhz 6 1/t clki internal clock frequency, clki (note 1) t clki = 1/(f clk /divide ratio) 3.072 6.144 mhz 6 t wch master clock high, clk 1 2, 3 38 20 ns 6 t wcl master clock low, clk 1 2, 3 38 20 ns 7 t sync sync period (master and slave modes) 128 * t clki 128 * t clki ns 7 t wsh sync high (slave mode) 20 126 * t clki ns c in input capacitance (except for left/right channel inputs) 20 pf master mode: i slav = 0 8 t sclk sclk period 2 * t clki 2 * t clki ns 8 t wl /t wh sclk duty cycle 0.667 1.50 8 t csy propagation delay (note 2) clk falling edge to sync clk rising edge to sync clk falling edge to sync 1 2 3 40 t clk + 40 2 * t clk + 40 ns ns ns 8 t csc propagation delay (note 2) clk falling edge to sclk clk rising edge to sclk clk falling edge to sclk 1 2 3 40 t clk + 40 2 * t clk + 40 ns ns ns 8 t cdv propagation delay (note 2) clk falling edge to serial data valid, sdo clk rising edge to serial data valid, sdo clk falling edge to serial data valid, sdo 1 2 3 40 t clk + 40 2 * t clk + 40 ns ns ns slave mode: i slav = 1 9 t su setup time (note 3) sclk to rising edge of clk 15 ns 9 t h hold time (note 3) sclk to rising edge of clk 0 ns 9 t sclkh sclk high 20 ns 9 t sclkl sclk low 20 ns 9 t su setup time (note 3) sync to rising edge of clk 15 ns 9 t h hold time (note 3) sync to rising edge of clk 0 ns t cdv propagation delay clk rising edge to serial data valid, sdo 1 2 3 t wch t clk t clk + t wch t wch + 40 2 * t clk + 40 3 * t clk + t wch + 40 notes: 1. the internal clock frequency, or input sampling frequency (clki) is governed by the divide mode and output data rate. the divide mode can be either 1, 2, or 3. the output data rate ranges from 24 khz to 48 khz. the minimum clock frequency of 3.072 mhz corresponds to an output data rate of 24 khz with the device in the clock divide by one mode. the maximum clock frequency of 18.432 mhz corresponds to an output data rate of 48 khz with the device in the clock divide by three mode. 2. propagation delay is measured with a capacitive load of 50 pf. 3. in the slave mode, sync or sclk transitions can occur anywhere except 0 to 5 ns relative to the clk rising edge.
MC145073 motorola 8 t wch clk, clki t clk , t clki t wcl figure 6. t wsh sync t sync figure 7. t wh t sclk t wl t csc t cdv t csy valid data clk/1 clk/2 clk/3 sclk sdo sync figure 8. serial interface timing (master mode: i slav = 0) t su , t h t cdv valid data sclk sdo sync clk/1 clk/2 clk/3 t sclkh t sclkl t su , t h figure 9. serial interface timing (slave mode: i slav = 1) note: clk signals shown above represent the external clock at three different frequencies.
motorola MC145073 9 pin descriptions analog pins a in(+l), a in(l) left channel analog inputs (pins 1, 2) these two pins comprise the left channel analog differ- ential inputs. the voltage range of signals applied to these pins is from v ss(a) to v dd(a) . a positive fullscale input to the a/d is defined as a difference of 3.8 v pp between a in(+l) and a in(l) . a in(+r), a in(r) right channel analog inputs (pins 24, 23) these two pins comprise the right channel analog differ- ential inputs. the voltage range of signals applied to these pins is from v ss(a) to v dd(a) . a positive fullscale input to the a/d is defined as a difference of 3.8 v pp between a in(+r) and a in(r) . ref output of the internal voltage reference (pin 3) the nominal value of this internal voltage reference is 2 v. the output of the reference is brought out to this pin to facili- tate filtering. for proper device operation, this pin should be decoupled to v ss(a) with a 1.0 m f electrolytic capacitor in parallel with a 0.1 m f ceramic capacitor. in order to economize on filtering capacitors, the ref pin can be connected to v ag . however, this could result in a possible degradation of performance of the device at high signal levels. v ag output of the internal analog ground generator (pin 22) analog ground is used to bias the internal analog circuits and is nominally 2 v. v ag is brought out to this pin to facilitate filtering. this pin should be decoupled to v ss(a) with a 1.0 m f electrolytic capacitor in parallel with a 0.1 m f ceramic capaci- tor for normal device operation. digital pins clk master clock input (pin14) this pin is the master clock input for the device. analog input signals to the MC145073 are sampled at a rate equal to this clock frequency divided by 1, 2, or 3, depending on the state of clock mode pins csel1,0. the serial data output rate is equal to the input sample rate divided by 128. for example, if clk is running at a 12.288 mhz rate, and divide by 2 is selected, then the output data rate is (12.288 mhz/2)/128 = 48 khz. for more detail, see the sum- mary of operating modes section. sync serial interface frame sync input/output (pin 11) the sync pin is an input or output depending on the state of the i slav pin. the sync signal resets and synchronizes the serial interface transmitter and receivers, as well as most internal clocks. left channel serial output data is transmitted when the sync signal is active high, and right channel data is transmitted when the sync signal is low. see the serial interface description section for more information. sclk serial interface clock input/output (pin 12) the sclk pin is an input or output depending on the state of the i slav pin. serial output data is clocked out of the MC145073 on the rising edge of sclk. when sclk is an input, it is reclocked by the internal sample rate clock, clki, before being used by the MC145073 to clock out the serial data. this reclocking ensures that rapid current changes through the sdo pin do not affect the analog performance of the device. see the serial interface description section for more information. sdo serial interface data output (pin 13) the a/d conversion results for the left and right channels are output on this pin. data is shifted out of the MC145073 msb first, with the left channel data preceding the right chan- nel data. the serial output data is clocked out on the rising edge of sclk. see the serial interface description section for more information. ftp factory test mode inputs (pins 9, 10) these pins should be connected to v ss(a) for normal device operation. csel0, csel1 clock divide mode select inputs (pins 21, 20) the device master clock input is divided by 1, 2, or 3, or the device is placed in a powerdown mode depending on the state of these pins. see the summary of operating modes section for more information. fsel fir filter response select input (pin 19) a low level on the fsel input selects a fir filter transition band from 20 to 25.8 khz at the 48 khz output data rate. a high level on the fsel pin selects a filter transition band from 20 to 24 khz at the 44.1 khz output data rate. see the sum- mary of operating modes section for more information. i sync serial interface sync format select input (pin 18) a low level input on the i sync pin selects a sync rising edge one sclk cycle before the initiation of a serial data transfer. a high level on the i sync pin will select a sync rising edge that is coincident with the initiation of a serial data transfer. see the summary of operating modes and the serial interface description sections for more information. i slav serial interface slave mode select input (pin 17) this pin controls the direction of the serial interface sync and sclk signals. a low level on the i slav pin will configure the sync and sclk pins as outputs, while a high level on the i slav pin will configure the sync and sclk pins as in- puts. see the summary of operating modes and the serial interface description sections for more information.
MC145073 motorola 10 i just serial interface data justification select input (pin 16) a low level on the i just pin will cause the serial output data to be left justified relative to the sync signal. a high level on the i just pin will select right justification of the serial output data. see the summary of operating modes and the serial interface description sections for more information. i doe serial interface data output enable (pin 15) this pin controls the state of the sdo pin between 16bit data word transfers. a high level on this pin will force the sdo pin to a low level between serial data words, while a low level on the i doe pin will force the sdo pin to a highimped- ance state between data words. see the summary of oper- ating modes and the serial interface description sections for more information. power supply pins v dd(a) (pin 4) positive analog power supply input. the voltage range for this pin is 4.5 to 5.5 v with respect to v ss(a) . the absolute value of the difference between v dd(a) and v dd(d) must not exceed 0.5 v. for proper device operation, this pin should be decoupled to v ss(a) with a 1.0 m f or larger capacitor. v ss(a) (pin 5) negative analog power supply input. this pin should be connected to ground for normal device operation. v dd(d) (pin 8) positive digital power supply input. the voltage range for this pin is 4.5 to 5.5 v with respect to v ss(d) . the absolute value of the difference between v dd(a) and v dd(d) must not exceed 0.5 v. for proper device operation, this pin should be decoupled to v ss(d) with a 1.0 m f or larger capacitor. v ss(d) (pin 7) negative digital power supply input. this pin should be connected to ground for normal device operation. sub (pin 6) substrate connection. this pin should be connected to v ss(a) for normal device operation. functional description the MC145073 is a 16bit stereo audio a/d converter in- tended for use in digital audio systems. the MC145073 uses a sigmadelta architecture consisting of a second order ana- log modulator followed by two stages of digital filtering for each channel. the analog modulator samples the input sig- nal at a very high rate (128x the output data rate), performs a single bit quantization, and shapes the quantization noise to- wards outofband frequencies. the digital filters of the MC145073 reject most of the shaped quantization noise, and lower the serial data output rate. the digital filtering is imple- mented with a 5 th order, decimateby32 comb filter followed by a 121 tap, decimateby4, fir filter on each channel. in addition to rejecting quantization noise, the fir filter cancels the curvature in the response of the preceding comb filter. the comb and fir filters also provide antialias filtering of outofband signals present at the input to the device. the analog inputs to the MC145073 can be fully differential (both inputs dynamic and 180 degrees out of phase), or singleen- ded (positive inputs dynamic while negative inputs are static at a level in the middle of the supply range). analog input sig- nals that exceed the differential analog input voltage range of 3.8 v pp are clipped in order to prevent overflow of the digi- tal filters. the MC145073 operates from a single 5 v power supply. for portable or other low power applications, a pow- erdown mode is available. the operation of the MC145073 can be tailored to specific applications by proper selection of the states of seven mode select pins. these mode pins control the divide ratio of the master clock, the fir filter response, and the serial interface format. the master clock input can be divided by either 1, 2, or 3 to yield the input sampling rate. this means that the in- put clock frequency is either 128x, 256x, or 512x the serial output data rate. note the oversampling ratio (osr), which is the ratio of input sampling frequency to output data rate, is 128x in all three cases. two sets of fir filter coefficients are stored in the on board rom of the MC145073. one set provides a transition band from 20 khz to 25.8 khz for operation at the 48 khz out- put data rate. the other set of fir filter coefficients provides a transition band from 20 khz to 25 khz for use with the 44.1 khz output data rate. four mode select pins configure the serial interface. this yields sixteen possible serial interface operating modes. included are modes that provide for interfacing directly to motorola and ti general purpose dsps, multiplexing of two MC145073s, as well as formats similar to the cs5326 inter- face.
motorola MC145073 11 summary of device operating modes the seven pins summarized in the tables below configure the MC145073 to operate in one of the modes specified. the modes can be chosen in any combination. csel1 csel0 master clk divider select 0 0 powerdown 0 1 divide clk by 1 1 0 divide clk by 2 1 1 divide clk by 3 fsel fir filter transition band select 0 20 khz 25.8 khz transistion band 6.144 mhz input rate, 48 khz output data rate. 1 20 khz 25 khz transistion band 5.6448 mhz input rate, 44.1 khz output data rate i sync serial interface sync signal format 0 sync rising edge is one sclk cycle before the start of the serial output data transfer. (this is compatible with the dsp5600/56001 and tms320 interface definitions.) 1 sync rising edge is coincident with the start of the serial output data transfer. (this is compatible with the cs5326 interface definition.) i slav serial interface master or slave select 0 MC145073 is a master, sync and sclk are outputs. 1 MC145073 is a slave, sync and sclk are inputs (reclocked by the MC145073 internal clock, clki). i just serial interface data justification select 0 serial output data is left justified relative to the sync signal. 1 serial output data is right justified relative to the sync signal. i doe serial interface data output enable 0 sdo goes to a highimpedance state between 16bit output words. 1 sdo is forced low between 16bit output words. serial interface description as summarized in the previous section, the format of the serial interface is controlled by four mode pins: i sync , i slav , i just , and i doe . these control inputs can be configured in any combination, yielding 2 4 = 16 unique modes. the follow- ing two subsections describe the format of the serial inter- face for these various modes. timing information for the serial interface is provided in the ac electrical specifica- tions section . compatibility with the dsp56000/1 and tms320 general purpose dsps is accomplished by applying the appropriate logic level to the i sync pin. the phase of the rising edge of the sync signal is different for the dsp56000 and tms320 applications, while the falling edge of sync is not critical in such applications. to interface to one or two MC145073s, the dsp56000/56001 should be configured as follows: network mode, four time slots per frame, 16 bits per slot, continuous clock, and control signals configured as either a master or slave. if interfacing to a tms320 is desired, the serial inter- face should be configured in continuous mode without frame sync. note the tms320 interface must be initialized with frame sync enabled, and then switched to the no frame sync mode after initialization. the i just and i doe serial interface mode control inputs are provided to facilitate multiplexing of two MC145073s. the i just input selects between left and right justification of the serial output data relative to the sync signal, while the i doe input provides a way to force the sdo pin to the high impedance state between the output data words. to multi- plex the serial data outputs of two MC145073s onto the same sdo line, i doe must be forced low on both MC145073s, while the i just pin is forced high on one MC145073 and low on the other. the MC145073s must be in the slave mode (i slav =1) when multiplexing. it is not pos- sible to operate with one MC145073 as a master tied to a second MC145073 operating as a slave due to the reclock- ing of the sync and sclk inputs in the slave mode (see operation with the MC145073 as a slave (i slav = 1 ) sec- tion). note when multiplexing two MC145073 devices, all four analog channels are sampled at exactly the same phase. in figures 10 and 11, the internal clock signal clki is plotted instead of clk. this is due to the fact that all internal clocks, as well as the serial interface, are slaved to this divided version of the master clock. input signals to the serial interface are reclocked by clki to reduce the amount of noise injected into the analog section of the MC145073. seri- al output data and highimpedance states of the sdo pin are clocked out relative to clki. this reclocking can cause a shift in phase of sdo relative to sclk when operating in the slave mode. in cases where the MC145073 output is multi- plexed with another device, the clock divide by 1 mode is recommended. note if the clock divide by 2 or 3 mode is selected, it is impossible to know the exact phase of clki. on initial powerup or recovery from a powerdown condi- tion, the first 68 serial output words of the MC145073 are indeterminate. this is because the digital filters and internal logic of the MC145073 must settle. this time is also used to charge the external ref filter capacitor.
MC145073 motorola 12 operation with the MC145073 as a master (i slav = 0) when i slav = 0, the sync and sclk signals are defined as outputs, and the MC145073 is configured as master device. in this mode there are eight possible serial formats as illustrated in figure 10. the phase of the sync output can precede the serial output data by one sclk cycle (com- patible with dsp56000/56001, tms320, and i 2 s interface format), or the sync signal can be coincident with the serial output data (similar to the cs5326 serial interface format). as shown in figure 10, with each of these two sync formats there are four possible formats for the serial output data. serial output data is shifted out msb first, with left channel data preceding the right channel data. all of the serial inter- face outputs, sync, sclk, and sdo are initiated by a clki rising edge. there are 128 clki cycles, and 64 sclk cycles per output data cycle. multiplexing of two MC145073s is not feasible in the master mode since the exact phase of the out- put cannot be controlled. note the serial data in one output cycle represents data that was simultaneously sampled on the two analog input channels. it is possible to initiate the device in the slave mode de- scribed in the operation with the MC145073 as a slave (i slav = 1) section, and then switch to master mode. once set, the phase of sync should not change. operation with the MC145073 as a slave (i slav = 1) when i slav = 1 the sync and sclk signals are defined as inputs, and the MC145073 is configured as a slave de- vice. however, the slave mode of the MC145073 is not a true slave mode since the sync and sclk inputs are reclocked by the internal sample clock, clki. these internal reclocked versions of sync and sclk are shown in figure 11, in addi- tion to the external sync and sclk signals. similar to the master mode of the previous section, there are two formats for the sync signal, and four sdo formats, yielding eight possible slave modes. multiplexing of two MC145073s in the slave mode is per- formed by forcing i doe low on both MC145073s, and forcing i just high on one MC145073 and low on the other. note when multiplexing two MC145073s, the mas- ter clock divide by 1 mode should be used (csel1,0 = 0,1) so that the exact phase of clki is determined.
motorola MC145073 13 clki sclk sync (isync = 0) sync (isync = 1) sdo (idoe = 0) sdo (idoe = 1) sdo (idoe = 0) sdo (idoe = 1) ijust = 0 ijust = 1 128 clki cycles 64 sclk cycles sample n sample n sample n + 1 sample n sample n sample n + 1 sample n sample n sample n sample n sample n 1 sample n 1 16 high z states 16 0's 16 0's d15l d14l d13l d1l d0l d15r d14r d13r d1r d0r d15l d14l d15l d14l d15l d14l d13l d1l d0l d15r d14r d13r d1r d0r d15l d14l d13l d1l d0l d15r d14r d13r d1r d0r d15l d14l d13l d1l d0l d15l d14l d13r d1r d0r d1r d0r d1r d0r 16 high z states 16 high z states 16 0's 16 high z states 16 0's figure 10. serial interface operation with MC145073 configured as master (i slav = 0)
MC145073 motorola 14 clki external sclk external sync sdo (idoe = 0) sdo (idoe = 1) sdo (idoe = 0) sdo (idoe = 1) ijust = 0 ijust = 1 sample n sample n sample n + 1 sample n sample n sample n + 1 sample n sample n sample n sample n sample n 1 sample n 1 d15l d14l d13l d1l d0l d15r d14r d13r d1r d0r d14l d13l d14l d13l d15l d14l d13l d1l d0l d15r d14r d13r d1r d0r d15l d14l d13l d1l d0l d15r d14r d13r d1r d0r d15l d14l d13l d1l d0l d15r d14r d13r d1r d0r d1r d0r d1r d0r internal sclk external sync internal sync internal sync isync = 0 isync = 1 16 high z states 16 high z states 16 0's 16 0's 16 high z states 16 high z states 16 0's 16 0's 128 clki cycles 64 sclk cycles figure 11. serial interface operation with MC145073 configured as slave (i slav = 1)
motorola MC145073 15 t 0.010 (0.25) a b m s s min min max max millimeters inches dim a b c d f g j k m p r 15.25 7.40 2.35 0.35 0.41 0.23 0.13 0 10.05 0.25 15.54 7.60 2.65 0.49 0.90 0.32 0.29 8 10.55 0.75 0.601 0.292 0.093 0.014 0.016 0.009 0.005 0 0.395 0.010 0.612 0.299 0.104 0.019 0.035 0.013 0.011 8 0.415 0.029 1.27 bsc 0.050 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. -a- -b- 112 24 13 -t- c k seating plane r x 45 g 22 pl p 12 pl 0.010 (0.25) b m m f j m d 24 pl dw suffix sog package case 751e04 package dimensions
MC145073 motorola 16 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.: spd, strategic planning office, 4321, p.o. box 5405, denver, colorado 80217. 3036752140 or 18004412447 nishigotanda, shinagawaku, tokyo 141, japan. 81354878488 mfax ? : rmfax0@email.sps.mot.com touchtone 6 022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, us & canada only 18007741848 51 ting kok road, tai po, n.t., hong kong. 85226629298 internet : http://motorola.com/sps MC145073/d ?

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